`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/03/29 09:15:43
// Design Name: 
// Module Name: data_ram
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module data_ram(
    input logic          clk,
    input logic          data_sram_en,
    input logic          data_sram_wen,
    input logic  [31: 0] data_sram_addr,
    input logic  [31: 0] data_sram_wdata,

    output logic [31: 0] data_sram_rdata
    );

    logic [31: 0] data[1023: 0];

    initial begin
        $readmemb("C:/Users/Tianlin/Desktop/data_mem.txt",data); 
    end

    always @(posedge clk) begin
       if (data_sram_wen) begin
           data[data_sram_addr] <= data_sram_wdata;
       end 
    end

    assign data_sram_rdata = data[data_sram_addr];

endmodule
